With FPGAs, it is possible to start using P4 data plane processing combined with the ease of software development on regular CPUs.
By now, all the professionals from the networking industry have heard of the recently announced Tofino chip prototyped by the Silicon Valley startup Barefoot Networks. Apart from offering 6.5 Tb/s throughput, the chip’s strength is that it should be programmable. This is made possible by P4 (Programmable Protocol-independent Packet Processor) programming language, an open source programming language designed around data forwarding.
If big players like Google, Facebook, or Microsoft decide to buy Barefoot’s chip en mass and build network switches and other proprietary hardware around it, it might become the next big thing that transforms the network industry. Moreover, there already is a way how to smoothly transition into this newly emerging ecosystem of P4-centered proprietary hardware. One can compile P4 into a programmable hardware like FPGA. With an FPGA mounted on a PCI-E network card it is possible to start using P4 data plane processing combined with the ease of software development on regular CPUs.
The full programmability of FPGAs takes the whole concept to a next step. It is not difficult to use P4 language in its current specification but it is also possible to extend the language by adding new features for different application use cases. To expand on P4’s functions is essentially like writing software. In the case of need it would therefore not be necessary to hire a hardware designer.
Speaking of programmability, P4 is very much in line with Network Function Virtualization (NFV), since the main goal of NFV is to bring similar disrupt networks as software virtualization brought to the world of computing. P4 enables rapid changes of the way packets are processed by the network and these changes are purely on a software side. Therefore, it is possible to deploy new network protocols, new services and applications using the hardware that is already in place.
P4 is also handy when it comes to traffic filtering. It does not allow to filter the traffic as selectively as a purpose-built firmware would, but it enables easy development of turn-key filters that correspond to the needs of the particular situation. These filters can be changed and reconfigured on a daily basis, making them suitable for network conditions of the day.
Possible use cases of P4 in NICs do not end here. Many data-forwarding processes can be simplified with P4: traffic en/decapsulation, orchestration with P4 switches by moving relevant part of traffic from switches to NICs, collection of traffic statistics and running server diagnostics, load balancing or traffic generation and traffic duplication.
What all these possible use cases have in common are these underlying benefits P4 offers: ease of implementation and reconfiguration coupled with P4’s separation of control plane from data plane and network architecture independence. And since it might become the programming language of the future in the field of data forwarding, backbone network operators should now be thinking about deploying a transitory solution that can work with current infrastructure, but is also P4 ready. This is where FPGA-based NICs shine.
Preliminary results of our full P4 processing pipeline running in FPGA. Apparently 100GE is just a start.
FPGA used during testing: Xilinx Virtex-7 H580T on Netcope 100G board.
Source: CESNET (Czech NREN)