Take a look at what Tradecope guys have been up to, we are moving forward! Reach us if you want to know more.
We are excited about our cooperation with Nagase. Combining ease of use of P4 for FPGAs with very efficient lookup engines makes packet processing in FPGAs easier and more effective than ever befor...
We are looking forward to meet you at MWC20 to discuss the hottest topics related to FPGA/P4 in the context of 5G mobile networks. Let's meet and talk not only about making mobile gateways more eff...
Smart Network Interface Cards (SmartNICs) can boost performance in mobile telecom networks. For 4G networks, SmartNICs can be used to implement many network functions in virtual machines or contain...
Představenstvo akciové společnosti Netcope Technologies, a.s., informuje o konání Valné hromady dne 26. 6. 2020, 9:30 hod.
Network Address Translation is a packet processing task, can consume a significant amount of CPU clock cycles which could otherwise be used for some useful operations. Fortunately, there is a way out.
We’re pleased to announce that Netcope P4 now also supports Intel® FPGA PAC N3000. Netcope P4 compiles the packet processing program written in open-standard P4 language into 100 Gbps FPGA firmw...
Fifth-generation (5G) mobile networks open one huge topic in accelerating mobile networks. Due to the replacement of the previous 4G technologies, networks are gradually upgraded with 5G equipment....
"Using P4, networking equipment architects can create high-speed, packet-processing pipelines even if they’re not experts or even familiar with FPGA-based design. Even experienced FPGA users will r...
Netcope P4 compiles the packet processing program written in open-standard P4 language into 100 Gbps FPGA firmware, allowing unprecedented flexibility and rapid development of high-speed network ap...
Automation of #FPGA design for computer networks. That's what defines #Netcope P4.
Netcope's CTO Viktor Puš explains details of valuable membership among Netcope Technologies and P4 Language Consortium. Read the whole interview.
Netcope has been cooperating with Silicom to introduce support of Silicom FB2CGG3 smart NIC in Netcope P4. Now, users of Silicom’s smart NIC can leverage the advantages and ease-of-use of Netcope ...
We have enriched Netcope P4 with packet duplication, registers, advanced match & actions tables and other new features.
Meet Netcope, Bell Canada, Cisco, Barefoot Networks and others at the 5th P4 Workshop
Petr Kaštovský will take part in a panel discussion on Innovation in Telecom Networking, NFV & Zero Touch World Congress.
In this demo we demonstrate how Netcope P4 programmable NIC used as INT Sink and Barefoot Deep Insight Analytics Software work together.
With Netcope Development Kit, it is possible to build a powerful 100G traffic generator for a much better price than a dedicated hardware generator.
Our long-term research partner CESNET has achieved impressive results in Suricata acceleration with NSF. Learn more about this and two other IDS use cases.
We have built and documented a PoC of Segment Routing at 100G Using FPGA Smart NIC and P4 Language. Learn more in our whitepaper.
A new VP of Sales bolsters our ranks and our CEO is temporary based in Silicon Valley, as we strengthen our position on US soil.
With our PCI-E FPGA cards, we have managed to overcome the PCI-E bottleneck. This means substantial cost savings for network operations, see calculations in the whitepaper.
The Netcope P4 is now officially online and it represents a paradigm shift in SmartNIC programming, making FPGAs much more accessible and cost effective.
Getting DPDK to receive and transmit packets at 100 Gbps is just a start. This whitepaper provides a theoretical model for understanding performance of high-bandwidth packet processing systems with...
Open vSwitch is a project that carried the NFV concept from its lab-only stage to the mainstream. And it can also be accelerated using FPGA technology.
We have hired a tech-dev veteran Viktor Puš to become the person in charge of our product development strategy, solidifying our position of a technological leader.
We have put together detailed test report of DPDK running on our NFB-100G2Q network interface card.
Netcope scales to 200G with the new low profile NIC equipped with Xilinx Virtex UltraScale+ FPGA chip.
We have joined the P4 Language Consortium, a community dedicated to standardization of one of the most innovative network technologies that has been developed in recent years.
Netcope demonstrates high degree of effectivity in building a production-ready solution through a clever mix of of hardware-accelerated probe and a network monitoring software.
Meet Netcope at P4’s Developer Day & Workshop to learn more about In-band Network Telemetry on 100G.
P4 enables reconfiguration of firmware without physical intervention. This, however, means that the API has to change as well. Read the detailed description on our P4 to FPGA compiler that generate...
Communication service providers benefit from effectively managed DPDK, because high DPDK throughput means fewer machines required. DPDK accelerated by NDP guarantees throughput of 148.8 Mpps.
Netcope Session Filter offloads predefined types of traffic in hardware and thus it unlocks the possibility to build a wire-speed solution for 100G traffic processing. The deluge of incoming data w...
On November 22 Netcope has won the Industria category for “the Most important innovative technology developed”. The name of the competition is the Česká hlava (“Czech Brain”).
Picomass uses Netcope Session Filter in IPS200 solution for Deep Packet Inspection, the main reason being that NSF is the only commercially available NIC capable of traffic filtering on per session...
In the last round of NFB and NIC tests, we have achieved 100 Gbps in both Rx and Tx. See preview of the report in the article or contact us and get the full report.
Good news for data center operators: Netcope Technologies now offers NFB-100G2Q, a new NIC with 2 QSFP28 optical interfaces.
Netcope Technologies takes part in a joint research project of Brno University of Technology and the Ministry of Interior of the Czech Republic.
We are glad to announce that we expand to the Japanese market, which is one of the world’s focal points of technological innovation.
Netcope Technologies hires tech-sales veteran Vladimír Reiff to lead our sales team.
We are going to exhibit in Prague, Tokyo and Frankfurt this June. Meet us there if you want to discuss our products face to face.
Combination of Cubro packet brokers and Netcope zero-loss packet capture solutions makes expense reduction with no network monitoring compromises possible.
We have been awarded 2nd place in the Cooperation of the Year competition for our participation in the project Distributed System for Complex Monitoring of High-speed Networks.
Our solutions are highly relevant in the world of finance and in the server community. The two conferences are dedicated precisely to these fields.
ISS World Middle East and OFC Conference are the places to be for those interested in network monitoring and security or high-speed Ethernet networking. We exhibit at both events.
The end of February and the beginning of March is a busy conference time for Netcope Technologies. We are attending RSA Conference 2016, Trading Show West Coast and Finam Conference Moscow.
Netcope Technologies announced a general availability of hardware-accelerated session processing solution – Netcope Session Filter (NSF).
Netcope Technologies, formerly Invea-Tech, now supports Intel DPDK interface in their FPGA-based network interface cards at wirespeed.
Netcope Technologies, the former FPGA department of INVEA-TECH, is proud to announce a new FPGA-based network interface card, the HANIC-100G2.
Netcope Technologies has released a second generation of TradeCOPE – ultra-low latency FPGA solution for electronic trading.
Preparing data centres for future security needs is the aim of the project recently started by Invea-Tech and the scientific team from the CESNET Association. Their goal is to develop the world’s f...
INVEA-TECH (now Netcope TEchnologies)in cooperation with CESNET demonstrated 100Gbps data transfers between FPGA chip and host memory over PCI Express bus. Such high throughput allows to build next...