Meet Netcope, Bell Canada, Cisco, Barefoot Networks and others at the 5th P4 Workshop
During the 4th P4 workshop, a group of thought leaders from Bell Canada, Cisco and Barefoot Networks presented the concept of “The Extensible Network: Evolution in Protocol and Data Plane Agility” leveraging IPv6 segment routing.
Segment Routing provides complete control over the forwarding paths of network traffic by combining simple network instructions. It does not require any additional protocol. Indeed in some cases it removes unnecessary protocols simplifying a network.
Inspired by their work, Netcope worked with Silicom and CESNET to make this concept real and created a demonstration of SRv6 functionality running at 100Gbps using a P4-programmable FPGA-based smart NIC. Visit the 5th P4 workshop to see the demo live.
Process of building a proof-of-concept that led to this technical demonstration has been described in the white paper “Building a PoC of Segment Routing at 100G Using FPGA Smart NIC and P4 Language”.
“Silicom recognizes the importance and possibilities with the P4 toolset. Segment routing is a prime example of a problem that is difficult to solve with conventional tools. We are excited to work with Netcope and leverage their advanced framework over our FPGA cards to address specific networking challenges and client needs.” says Elad Blatt, Chief Strategy and Business Development Officer at Silicom.
"The advent of a programmable protocol architecture such as SRv6 and network programming, combined with the capabilities offered through open programmable data planes and P4 really extends the data plane boundaries. This demonstration by Netcope truly highlights how we can now implement a reference behavior in hardware or be creative and create new ones without having to create a completely new encapsulation." sais Daniel Bernier, Network Strategist of Bell Canada.
“The idea of using P4 to implement segment routing immediately caught our attention. It allowed us to demonstrate the strength of the P4 language to express packet processing as well as the efficiency of our compiler and FPGA implementation that achieved the performance of 100Gbps in a PCIe network interface card.”, said Petr Kaštovský, CEO of Netcope Technologies.