We are excited about our cooperation with Nagase. Combining ease of use of P4 for FPGAs with very efficient lookup engines makes packet processing in FPGAs easier and more effective than ever before. Read more in the article.
Deployments of 5G networks, continuous build-out of data centers those are only two example drivers for fast, flexible and programmable network infrastructure. The complexity of applications led to the invention of programmable networks that can keep up with the innovation pace driven by software. On the other hand, the need for efficient and low latency execution is pushing the programmability into the hardware. The FPGA chips sit on the boundary of software programmability and hardware-like execution efficiency.
The downside of FPGAs is the design entry barriers due to complex programming languages. Such barriers can be addressed by leveraging higher-level languages like P4 for networking specific workloads. P4 language not only abstracts the details of the hardware target but also supports various types of operations, tables, rules and constructs that are required by modern networking workloads.
Netcope and Axonerve have worked together and integrated Netcope P4 packet processing pipeline with Nagase Axonerve lookup engines. The integration has been done for Intel Stratix 10 FPGAs offering HBM2 memory which in turn provides large capacities of high-bandwidth memory that is able to keep up with the most demanding requirements.
"Axonerve is an algorithmic lookup engine with great scalability, high throughput, and ultra-low latency. Programmability and high performance are the most important parameters of P4-FPGA solution and that drives the cooperation of Netcope and Axonerve."
Kaoru Kobayashi, Marketing manager at Nagase
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