Getting DPDK to receive and transmit packets at 100 Gbps is just a start. This whitepaper provides a theoretical model for understanding performance of high-bandwidth packet processing systems with FPGAs and CPUs.
With the 100 Gigabit Ethernet being mature and available technology, as well as 400 Gigabit Ethernet standard just before finalization, it seems that CPUs have a hard time trying to catch up. We have already demonstrated that receiving and transmitting full 100GE line rate in a single-CPU server with FPGA-based NIC is entirely possible, but that doesn’t tell much about the usability of such setup from the application perspective.
Read the whitepaper here.
The goal of this paper is to understand exactly what are performance limitations of CPUs, how can we measure, describe and compare them, and what can we do to overcome the limitations.