In the field of Ultra-low latency or High-frequency trading (HFT), primary focus is on the execution speed of trading algorithms. Therefore, FPGA providing much faster accelerated execution than CPU processors, represents a more suitable and more profitable platform for execution of trading algorithms.
Up to the present, most trading algorithms have been implemented using C/C++ code, because by writing algorithms in C/C++ traders can get the best performance out of their trading machine, considering the complexity of the trading algorithm specification. But for a long time the limitation of C/C++ code has consisted in the platform selection, because only standard CPU processor compilers were available.
On the other hand, Field Programmable Gate Array (FPGA) circuit, as an alternative platform today, offers significantly lower latency compared with processors. But the standard FPGA development process requires an algorithm to be written in Hardware Description Language (HDL), which is based on different design principles than C/C++.
Vivado HLS is a compiler that translates the C/C++ code directly into HDL code appropriate for FPGA. As a consequence, a trading algorithm written in C/C++ can be re-targeted to FPGA without knowledge of any HDL. It means, the C/C++ code is used in software during simulation and also as an input during translation to HDL code. Furthermore, no special knowledge of the FPGA domain is required.
Want to read more? Download the whole whitepaper.