General NIC Functionality IP Cores

Ethernet & MAC layer IP core

The IP core covers the MAC layer and the necessary parts of PCS and PMA layers for 100G, 40G, and 10G Ethernet technologies. It interfaces with Xilinx's GTZ or GTH transceivers that communicate with optical modules over multiple 25G or 10G channels on one side and with user components on the other side. The interface on the user side is comprised of an easy-to-use high-speed point-to-point bus compatible with AXI4-Stream bus and a low-speed configuration bus compatible with AXI4-Lite bus. The IP core implements all important features of the MAC layer and is implemented according to the IEEE 802.3 standard.

PCI Express & DMA engine

The IP core implements a high-performance DMA engine over the PCI Express bus. It interconnects the software layer with the hardware application core through several DMA channels using easy-to-use high-speed point-to-point bus compatible with AXI4-Stream bus. Software layer can be used with Intel DPDK API, PCAP API, highest-performance proprietary API, and standard Linux network interface incorporating Linux TCP/IP stack. The number of DMA channels in each direction is independent and can be adjusted. PCI Express Gen 3 x16 is supported using two PCI Express Gen 3 x8 endpoints in the FPGA chip and the PCI Express bifurcation feature of the chipset of the host machine. Sustainable throughput of more than 100Gbps of user data is supported in both directions simultaneously.

Time Synchronization IP Core

The IP core serves as a source of precise time information with nanosecond precision for firmware components. It is synchronized and syntonized based on the external PPS (pulse per second) signal, which can be obtained e.g. from a GPS receiver or any distribution point of a PPS signal. An example of a use case of the IP core is latency measurement or assignment of timestamps to incoming frames. Its resolution allows to distinguish between two shortest successive Ethernet frames on a 100G Ethernet link.

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