NETCOPE P4 - FLEXIBLE FPGA PROGRAMMING

REDUCES TIME TO MARKET FOR FPGA-BASED NETWORKING APPLICATIONS BY A FACTOR OF 10

Netcope P4 is a cloud-based platform for easy development of packet processing pipelines for FPGAs using a high-level open-source language P4. It enables networking software developers, engineers, and equipment manufacturers to leverage FPGAs without the need to understand the internals of the chip while reducing time to market by a factor of 10.

 

Netcope P4 cloud Download Netcope P4 product brief

Features & Benefits

  • Programmable protocol stack

  • User-defined packet processing

  • No FPGA expertise needed

  • No synthesis tools or servers needed

  • Firmware as a Service

  • User-friendly online portal

  • Efficient P4 to FPGA implementation

 

Use Cases

  • Accelerated Network applications

    • ​Mobile Network Gateway (EPC/5GC)

    • Broadband Network Gateway (BNG/BRAS)

    • Segment routing (SRv6)

    • Virtual switch offload​

  • Network troubleshooting and fine-tuning

    • In-band Network Telemetry (INT)

    • In-situ Operations, Administration and Management (iOAM)

  • ​Network traffic preprocessing

    •  Encapsulation/decapsulation

    •  Tunnel termination

    •  Receive-Side Scaling (RSS)
    • ​ Load balancing

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APPLICATIONS

Mobile and Broadband Network Gateways

Mobile and Broadband Network Gateways

Mobile and broadband network gateways are a popular choice for offload in smart NICs. There are obvious reasons for this approach as the workload of CPU cores becomes too high because of the increasing amount of traffic, leaving less performance for virtual machines or containers. Netcope P4 is being used to describe the offload of functions of the core network (4G EPC and 5GC) including packet encapsulation/decapsulation, packet filtering, flow-based charging, NAT and others.
NFVI Acceleration

NFVI Acceleration

In order not to burden CPU cores with virtual switching and let them be used for virtual functions themselves, smart NICs are being used to offload classification and forwarding. Netcope P4 offers a flexible way of the definition of the classification rules or SRv6 functions that are performed directly in hardware. E.g. Open vSwitch offloads its microflow and megaflow caches so the majority of the traffic does not reach CPU cores at all.

 

Netcope P4 in action

EPC and INT

EPC and INT

At ONF Connect 2018, Netcope P4 has been used to program FPGA-based 2×100G programmable smart NICs to perform GTP tunnel encapsulation and decapsulation on the emulated mobile traffic to demonstrate the possibility of offloading S/P-GW functionality while simultaneously applying in-band network telemetry to observe the behaviour of the traffic and the performance of the network.
Virtualized BNG

Virtualized BNG

Running vBNG as the workload of compute nodes is one of the proposed options for the SEBA Exemplar Platform. The talk given at ONF Connect 2019 explored what options there are to improve performance parameters of such application with P4 programmability and FPGA SmartNICs.
Segment Routing

Segment Routing

Presented on multiple events including 5th P4 workshop at Stanford University and Interop Japan 2019, the demo of segment routing over IPv6 shows the options of the P4 language to be used for hardware offload of the segment routing functions on high-speed networks.
In-Band Network Telemetry

In-Band Network Telemetry

Following the success at MWC 2018 in Barcelona, Open Networking Foundation has invited Netcope Technologies and Barefoot Networks to extend ONF’s CORD demonstration with some more P4 and In-Band Network Telemetry. Working closely with ONF as well as Barefoot engineers, Netcope was able to easily integrate their P4-programmable NICs to play valuable roles within the network infrastructure.

Supported platforms

IntelⓇ FPGA PAC N3000
4 x 25G / 8 x 10G card by Intel. This SmartNIC features Arria 10 FPGA connected as a "bump in the wire".
Silicom FB2CGG3
2x100G card manufactured by Silicom. Ready for up to 2 QSFP28 transceivers, Virtex Ultrascale+.
SILICOM fb2CGhh
2x100G card manufactured by Silicom. Ready for up to 2 QSFP28 transceivers, Kintex UltraScale+.
Xilinx Netlist
Xilinx Netlist
Netlist for Xilinx Virtex-7, UltraScale and UltraScale+ FPGAs. To be integrated with the hardware platform of your ch...
Intel Netlist
Intel Netlist
Netlist for Intel Arria 10 and Stratix 10 FPGAs. To be integrated with the hardware platform of your choise.

References

Silicom recognizes the importance and possibilities with the P4 toolset. Segment routing is a prime example of a problem that is difficult to solve with conventional tools. We are excited to work with Netcope and leverage their advanced framework over our FPGA cards to address specific networking challenges and client needs.

Elad Blatt, Chief Strategy and BDO at Silicom.

The advent of a programmable protocol architecture such as SRv6 and network programming, combined with the capabilities offered through open programmable data planes and P4 really extends the data plane boundaries. This demonstration by Netcope truly highlights how we can now implement a reference behavior in hardware or be creative and create new ones without having to create a completely new encapsulation.

Daniel Bernier, Network Strategist of Bell Canada

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