P4 to VHDL

Although one of the goals of P4 language is independence of target architecture, not all of them offer the same possibilities in terms of flexibility and performance. The advantage of FPGAs is their full programmability. There is no limitation in functionality that can be incorporated into the firmware and performance is still predictable. Symbiosis of P4 and FPGAs ensures network data processing at 100Gbps without any packet loss still using a simple way of description in a high-level language.

Download P4 to VHDL Detailed Description

P4-Diagram-(1).png

P4-to-VHDL compiler is based on market-proven IP cores that are used in Netcope’s products. Configurable packet header processor is used for parsing network protocol headers and TCAMs and hash or trie-based data look-up IP cores are used for match&action tables. Generated firmware uses network modules for 100G, 40G, and 10G Ethernet, PCI Express bridge and DMA modules with sustained 100Gbps throughput. Each IP core is fine-tuned for optimal performance to guarantee wire-speed traffic processing regardless of packet length.

P4-to-VHDL compiler uses Netcope Development Kit (NDK) as a platform for synthesis of resulting firmware. It puts the abovementioned IP cores together and interconnects them according to P4 description with possibility to include additional, or third-party, IP cores like encryption or pattern matching. In combination with other technologies delivered together with NDK like DPDK and SR-IOV support, it lays solid foundations for deployment in NFV (network functions virtualization) environment.

Features & Benefits

  • easy programmability of network data plane

  • possibility to extend P4 language capabilities

  • abstract description of packet processing in FPGA

  • significantly reduced time to market for network updates and upgrades

 

Use Cases

  • network function virtualization

  • programmable protocol stack

  • easy support of network overlays

  • user-defined packet processing

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