P4 to VHDL

P4 is a high-level language for programming protocol-independent packet processing. It has been defined in order to enable easy programmability of network data plane processing agnostic to underlying technology, e.g. ASIC, CPU or FPGA. Our framework automatically generates VHDL source code from P4 sources. So user can easily describe how they want to process packets in the P4 language and then use this framework to get a VHDL implementation of such processing.

Download P4 to VHDL Detailed Description

P4-Diagram-(1).png

FPGA programmable hardware is great at performing SIMD type processing (single instruction, multiple data) with excellent performance per watt. This makes FPGAs a perfect fit for use in network data plane processing acceleration. On the other hand, FPGAs are demanding for programming them. Before P4, it was necessary to have a grasp of low level programming languages like VHDL or Verilog.

P4 in FPGA is a strong combination of high-level programming of network data plane processing for a programmable hardware target (FPGA) that offers excellent performance per watt and enables rapid development of new network solutions without the need of being an FPGA engineer. Simplified programmability paves the way to innovation and network function virtualization (NFV).
 

Features & Benefits

  • easy programmability of network data plane

  • possibility to extend P4 language capabilities

  • abstract description of packet processing in FPGA

  • significantly reduced time to market for network updates and upgrades

 

Use Cases

  • network function virtualization

  • programmable protocol stack

  • easy support of network overlays

  • user-defined packet processing

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