Lower the latency of your trading system with Tradecope

Together with automated trading systems, the evolution of high-frequency trading is significantly increasing the requirements for trading systems’ latency. Netcope Technologies offers a solution to minimize latency by off-loading tick-to-trade execution into fast FPGA hardware. Tradecope is the first easy-to-use, ultra-low-latency trading system that allows anybody to benefit from pure hardware trade processing without the need for FPGA expertise or a hardware designer.

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*white paper: Acceleration of trading algorithms with Tradecope



TradeCope Features

  • Input traffic filtering

  • A-B channel arbitrage

  • Sequence number gap detection

  • Sending of orders to market

  • Message and symbol filtering

  • Pre-trade risk check

  • Computation of pre-defined statistics (EMA, MID, etc.)

  • Trading strategy triggered by market update

  • Building of order book representation
    in the FPGA

  • FIX/FAST and binary decoding


The performance of software implementations of feed handlers, trading-strategy logic and order generation usually shows a slowdown caused by the operating system running on the machine. There are several clear latency bottlenecks on virtually every common system running an OS.

Tradecope successfully overcomes these latency bottlenecks by implementing a tick-to-trade engine directly in FPGA hardware:

  • The whole FPGA hardware is fully dedicated to the trading system; there are no unnecessary tasks consuming the hardware’s processing power.

  • The network communication containing market data does not need to be forwarded to the software, but instead is processed inside the FPGA network interface card, thus eliminating OS kernel network stack latency and the latency of PCIe transfers.

  • True parallelism is a natural feature of FPGA hardware, which can handle many distinct jobs at the same time.

Low-latency solution for algorithmic and high-frequency trading based on high performance FPGA hardware

  • Pure hardware performance. The whole trading pipeline from receiving market data, through packet arbitration, message decoding, book building, trading strategy execution, risk check and order generation is implemented and runs directly in the hardware. This allows us to fine tune every single processing step and achieve sub-microsecond tick-to-trade latency.

  • Easy to use. The user is abstracted from the FPGA internals and hardware specific details and can use Tradecope as if it were a software solution. This level of abstraction enables anybody to use Tradecope and benefit from pure hardware processing. It allows a quantitative analyst, equity trader or anyone else to focus on the trading strategy without the need to worry about low-level programming, market data formats or digital hardware design.​

  • Strategies and API in C++. ​We provide a latency-optimized API allowing the user to easily communicate with the card and build software routines for further management of trading behavior. The latency-insensitive part of the trading strategy should run on the CPU to keep the latency-sensitive part in the FPGA as fast as possible. Using the optimized API, the software can send parameters to the logic in the FPGA to modify its behavior on the fly.

  • Write your decision logic in C/C++. From the end user’s point of view, the only requirement is to provide decision-making logic written in the C/C++ language (or optionally in HDL). This code is automatically transformed into a hardware representation and connected to the hardware pipeline in the FPGA. After that, Tradecope is ready to trade. This includes statistics gathering, trading parameter updates and offloading of the latency-insensitive parts of the trading strategy to the CPU to keep the latency-sensitive part in the FPGA as fast as possible.

  • Deliverables. . Tradecope is delivered as a hardware/software solution composed of an FPGA network interface card, appropriate firmware with card management tools, and an API with examples of software applications. The modularity of Tradecope allows us to create turnkey solutions for our customers and/or supply only specific IP cores necessary for a particular customer’s requirements.

  • Support. Netcope Technologies is able to provide you with assistance in implementing your solution as well as further customizations above the standard level. It is possible to arrange an evaluation period to accommodate in-house testing and PoC in the customer’s environment.

Thanks to the adaptability of Tradecope, it can be used in many different scenarios to fit a specific customer requirement

  • Data filtering.Incoming packets can be filtered according to their IP addresses and ports and perform A/B channel arbitrage. More advanced features include filtering of decoded messages according to the symbol ID or the message type. Combinations of the above-mentioned features are also possible.

  • Framework for implementing trading strategies. Tradecope provides a framework for implementing trading strategies in a high-level programming language. The user code is automatically transformed into an FPGA representation. Together with the accelerated feed handler and order sender unit, Tradecope is able to process market data and send orders back to the market. As the whole pipeline is implemented in the hardware, it achieves sub-microsecond latency and deterministic behavior.

  • Pre-trade risk checks and TCP injection. Tradecope includes cores for the processing and decoding of order entry protocols, which makes it possible to perform wire-speed risk checks in the high-performance FPGA chip in a manner that is transparent to the user. A packet with an order may be dropped if risk checks do not pass or a TCP packet may be injected if a specific event is detected. For instance, it is possible to specify thresholds for open positions and traded volume. Tradecope is able to cancel orders on the book with ultra-low latency when the threshold is breached.

  • Accurate market data recording & replaying. As Tradecope is based on a high-performance FPGA network interface card with an external connector for time synchronization, it enables traffic recording and replaying while preserving traffic time-characteristics with nanosecond precision.

  • Data normalization. Tradecope can be used as a universal decoder for different market feeds. Both FIX/FAST and binary formats are supported. Output from the decoder is normalized and a highly optimized API offers a fast way to stream data to the user application.

  • Accelerated feed handler. Tradecope processes market data directly (filtering, decoding) in the FPGA and creates an order book. Predefined statistics are computed as well. All the data are accessible from the software using a highly optimized API.

  • Accelerated order sending. Tradecope may be used as a fast order generator and sender. Thanks to its unique HW/SW co-design and complete OS kernel bypass, maximum acceleration of order sending is achieved. Various market protocols are supported, e.g. FIX, Arca Direct and OTTO.

"“The process of moving our trading strategy to the TradeCOPE platform was very smooth even though we did not have any previous experience with FPGA technology. The solution is easy to use and the guys were very helpful. After their initial assistance and introduction to the framework, we were able to maintain and update trading strategies ourselves. We have doubled our hit rate in a month and significantly increased our profits. The product literally paid for itself in no time.”“

Head of technology at U.S. based trading company

Learn more about this deployment in our Case Study

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