Low-latency Electronic Trading

In algorithmic and HFT trading, a good strategy is only half of the solution. The strategy needs a platform that would execute it. Software platforms offer flexibility at the cost of latency and jitter. High latency with jitter means missed opportunities and possible losses. Hardware platforms offer high performance and superior latency, but it is challenging to implement and readjust the strategy once the hardware platform has been deployed. Needless to say it is undesirable to reveal the strategy to a third party, whose help is often required when programming the hardware.

There is a way of achieving both ease of implementation of the strategy and low, deterministic latency: embedding the strategy in an FPGA network card. A shining example of this approach is Tradecope. Tradecope implements the full tick-to-trade pipeline in FPGA and allows implementing the trading strategy in the C++ language. This means that any software engineer can embed the strategy without the need to disclose it to the third party. Its FPGA-based hardware platform leverages deterministic latency below 1 μs. It is a complex bundle of HW, FW and SW perfectly suited for any algorithmic and HFT strategy.